1. Field of the Invention
The present invention relates to a level shifter, and more particularly, to a level shifter circuit which can make an efficient level shift to level up or level down according to a change of a digital logic characteristic.
2. Background of the Related Art
Either level up or down by the level shifter is determined according to a digital logic of the level shifter input/output, according to which a level shifter circuit is designed. A related art level shifter will be explained with reference to the attached drawings. FIG. 1 illustrates a system of a related art level shifter circuit, and FIG. 2 illustrates a graph showing a related art voltage transfer characteristic.
Referring to FIG. 1, the related art level shifter is provided with a first NMOS transistor MNI having a gate for receiving a digital logic signal, an inverter buffer INI for receiving the digital logic signal and determining an output switching point for the digital logic signal, a second NMOS transistor MN2 having a gate for receiving an output from the inverter buffer IN1, and a first and a second PMOS transistors MP1 and MP2 having gates for receiving outputs from drains of the first and second NMOS transistors MN1 and MN2 serving as active loads for the first and second NMOS transistors MN1 and MN2.
The operation of the related art level shifter will be explained. The operation of the level shifter can be known efficiently when a state of an output voltage Vout, i.e., an output state of an input voltage Vin provided to a gate of the first NMOS transistor MN1 after being swept is reviewed. That is, the voltage transfer characteristics are as follows.
Referring to FIG. 2, when the input voltage Vin is at low, the output voltage is also at low. In this state, if the input voltage is increased, a Vgs of the first NMOS MN1 is increased, causing a current flowing through the first NMOS transistor MN1 to increase. Though the current flowing through the first NMOS transistor MN1 is increased, the output voltage shows no substantial increase compared to a prior voltage. There is no substantial increase in the output voltage Vout because an output from the inverter buffer IN1 shows no substantial change if an input to the inverter buffer IN1 is increased over the low level(a level of the Vin received presently), which output is connected to the gate of the second NMOS transistor MN2 thereby causing no substantial change in the current flowing through the second NMOS transistor NM2. If the input keeps increasing from this state to a state higher than the low level but lower than a high level, the inverter buffer IN1 is operative in a transition region, decreasing the current flowing through the second NMOS transistor MN2. If the current flowing through the second NMOS transistor MN2 is decreased, the Vgs voltage of the second NMOS transistor MN2 is lowered to boost the output voltage Vout. That is, the decrease of Vgs of the first PMOS transistor MP1 further decreases the current flowing through the first PMOS transistor MP1, that further decreases a voltage between the drain-source of the first NMOS transistor MN1. When this case is occurred, the current flowing through the second PMOS transistor MP2 is further increased, accelerating increase of the output voltage faster to a high voltage. Thus, the first PMOS transistor MP1 and the second PMOS transistor MP2 vary output voltage levels with logic state changes of the input voltage Vin in the level shifter circuit.
However, the related art level shifter circuit has the following problem because level up or down is determined according to a digital logic of the level shifter input/output, according to which the level shifter circuit is designed. That is, if input and output digital logic characteristic is changed from a level up to a level down or vice versa, the present level up shifter(or a level down shifter) should be re-designed.